1. Field of the Invention
The present invention generally relates to a semiconductor device and a method for manufacturing the same and, more specifically, to a semiconductor device with a moisture-proof ring and a method for manufacturing the same.
2. Description of the Related Art
In semiconductor devices in recent years, with miniaturizatation and high integration, a multilayer wiring structure, in which a plurality of interlayer insulation films are layered in each of which a wiring pattern is embedded, is often used to connect many semiconductor elements to each other on a common substrate. In such a semiconductor device, moisture or corrosive gas may enter the inside of the semiconductor device along the interface between the interlayer insulation films constituting the multilayer wiring structure, and thus it is generally performed to form in the multilayer wiring structure a moisture-proof ring along the peripheral portion of the substrate to intercept entry of moisture or corrosive gas.
In semiconductor devices in recent years, with miniaturization and high integration, the design rule becomes smaller every year, giving rise to a technical limit in a method of forming a metal wiring material by direct etching. Hence, a start has already been made at using a damascene method which forms in an interlayer insulation film a wiring pattern and a via contact, or both a wiring pattern and a via contact by a photolithography method in advance, and then embeds a wiring material and polishes it using a CMP (chemical mechanical polishing) technology to form a wiring pattern and a via contact.
Specifically, in a recent highly miniaturized semiconductor device including a semiconductor device in submicron or subquarter-micron size, Cu (copper) having low resistance as a conductor pattern is used in combination with an organic interlayer insulation film having low dielectric constant to avoid signal delay occurring in the multilayer wiring structure. In this event, Cu is hard to be dry-etched unlike Al, W or the like which has conventionally been used for a conductive pattern. Therefore, a dual damascene method is often used which forms in advance a wiring groove and a contact hole in an interlayer insulation film, and deposits a Cu layer by an electrolytic plating method or the like to fill the wiring groove and the contact hole as described above.
Generally, when the damascene method is used, a stopper and diffusion preventing film is formed between a lower interlayer insulation film and an upper interlayer insulation film to prevent diffusion of Cu and improve controllability in a direction of the depths of a wiring pattern and a contact hole.
FIG. 1 shows an example of a conventional multilayer wiring structure.
Referring to FIG. 1, after formation of a circuit element 4 on a semiconductor substrate 60 supporting an insulation film 10 and a via contact plug 70, an interlayer insulation film 11 is formed. On the interlayer insulation film 11, a not-shown photoresist film is applied, further, exposed to light, and developed to pattern the photoresist film into the shape of a wiring pattern 41. The interlayer insulation film 11 is then etched with a resist pattern (not shown) thus formed as a mask into the shape corresponding to the wiring pattern 41 desired to be formed, and a barrier metal film 31 is formed inside the wiring pattern 41. Further, the wiring pattern 41 is embedded thereon. Polishing is then performed using a CMP method to form the wiring pattern 41. Such a method is called a single damascene method. Incidentally, a via contact is composed of an adhesive film 70b covering the wall face inside a via hole and a metal film 70a formed on the adhesive film 70b. 
After the formation of the wiring pattern 41, a stopper film and diffusion preventing film 21, an interlayer insulation film 12, an etching stopper film 22, and an interlayer insulation film 13 are sequentially formed. A not-shown resist is then exposed to light and developed on the interlayer insulation film 13 into the shape of a via pattern 51 desired to be formed. Etching is performed with a formed resist pattern as a mask until the top face of the stopper film and diffusion preventing film 21 is exposed. Another not-shown photoresist film is then applied, exposed to light, and developed to form a resist pattern which corresponds to a wiring pattern 42. The interlayer insulation film 13 is then etched with the resist pattern as a mask until the top face of the interlayer insulation film 12 is exposed.
In this event, the bottom portion of the via pattern 51 is concurrently etched to the top face of the wiring pattern 41. Further, a barrier metal film 32 is formed inside the wiring pattern 42 and inside the via pattern 51. A material for the wiring pattern 42 is further embedded therein. Polishing is then performed using the CMP method to form the via pattern 51 and the wiring pattern 42. Such a method is called a dual damascene method.
Typically, in manufacturing a semiconductor device such as an LSI or the like, after a wafer process of forming many semiconductor devices at once, a wafer is cut along scribe lines defining each semiconductor device in a dicing step so that the semiconductor wafer is separated into individual semiconductor devices or chips.
FIG. 2 shows a top view of a conventional semiconductor device. One-dotted chain lines 3 in FIG. 2 show portions to be diced. The dicing is performed along the outer peripheral portion of a semiconductor device 1.
Referring to FIG. 2, the semiconductor device 1 is formed with a moisture-proof ring 2 for preventing occurrence of cracks in dicing and intercepting entry of moisture or the like into the inside of the semiconductor device 1 for prevention of a decrease in yield of the semiconductor device 1, in such a manner that the moisture-proof ring 2 continuously surrounds the outer peripheral portion of the semiconductor device 1.
As a method of preventing the cracks and entry of moisture or the like, for example, a structure and a process shown in FIG. 3 are disclosed in Japanese Patent Laid-Open No. 2001-53148.
FIG. 3 shows a conventional moisture-proof ring structure.
Referring to FIG. 3, in forming wiring patterns and via contacts of a circuit portion, after formation of an interlayer insulation film 531 on a semiconductor substrate 501, a contact pattern 521 composed of an adhesive layer (not shown) and W is formed. A wiring pattern 541 composed of an AlCu layer which is vertically sandwiched between not-shown TiN/Ti layers is then formed above the contact pattern 521. Subsequently, after formation of an interlayer insulation film 532, via patterns 522 composed of an adhesive layer (not shown) and W are formed to the top face of the interlayer insulation film 531, at both ends of the wiring pattern 541 in a manner to be offset to the outside.
Subsequently, a wiring pattern 542 is processed direct on the via patterns 522, and an interlayer insulation film 533 is formed. Via patterns 523 composed of an adhesive layer (not shown) and W are formed at both ends of the wiring pattern 542 in a manner to be offset to the outside, using the same technique as that in forming the via patterns 522. Further, the whole from the top face of the semiconductor substrate 501 to the lower face of the interlayer insulation film 533 being the uppermost layer is covered with a TiN film or the like resistant to moisture or the like, thus forming a barrier structure.
In the structure of FIG. 3, a moisture-proof ring can be effectively formed by layering metal patterns excellent in adhesiveness. For employment of this method, however, the wiring material is limited to a material such as Al—Cu capable of being etched. This method is not applicable to a multilayer wiring structure including Cu wiring patterns which need to be formed by the damascene method. Such a structure is not formed either.
In the conventional dual damascene structure as shown in FIG. 1, there is a region not in contact with the via pattern 51 at the top of the wiring pattern 41 on a scribe line side 80. At the region, the stopper and diffusion preventing film 21 is in contact with the surface of the wiring pattern 41. Generally, an insulation film such as a SiN, SiC film or the like is used for the stopper and diffusion preventing film 21. The insulation film, however, has poor adhesiveness with a metal film in use for the wiring pattern 41. This causes a problem that the insulation film cannot prevent cracks at the interface between the insulation film and the wiring pattern 41 nor secure moistureproofness when moisture or the like enters.
Additionally, in the dual damascene structure as shown in FIG. 1, Cu is used as a wiring material. Cu, however, is hard to be patterned by etching, and thus the method shown in FIG. 3 is not applicable as described above.